| 摘要 |
Disclosed is an integrated circuit device enabling the computation of multiplication of A by B, especially a computation of the Pfield(A,B)N type as defined in the Montgomery method, using a subdivision into words of Bt bits to carry out the different computations. This device is improved by the addition of a register of m * Bt bits containing the totality of the data element A. The invention also relates to a device for the implementation of a modular Pfield(A,B)N operation according to the Montgomery method using the improved device presented by the invention.
|
