SEMICONDUCTOR STORAGE CIRCUIT

摘要

PROBLEM TO BE SOLVED: To shorten test time and also to enhance the productivity by making items of an error-correcting code generating logic odd numbered terms and changing the address arrangement of a bit map to enable check data to be written in a user area and a correcting area simultaneously. SOLUTION: In a semiconductor memory circuit having the error correcting circuit of storage data, a logic generating a 6-bit error-correcting code is composed of 15 terms of D00 to D31. The address arrangement of a bit map is made an address arrangement capable of writing check data for bit interference of test data in a user area and an ECC area simultaneously by making it a prescribed bit map address continuation while making values of outputs 00 to 05 high levels all or low levels. Thus, a write time at the time of checking bit interferences of ROM cells and a test time are shortened and also even when the defective bit of one bit is present in the 6 bits of the ECC, the ROM is not erroneously judged as a defective product and the yield is enhanced.