| 摘要 |
<p>PROBLEM TO BE SOLVED: To select the waveform of an output clock signal by combining the resistance value of a clock driver and the load capacitance value and selecting a time constant. SOLUTION: A driver circuit 100 includes the CMOS transistors TR 110, 120 and 130. A combinational logic circuit of AND gates 111, 121 and 131 is connected to the gates of PMOS and NMOS TR 112, 122 and 132 and 113, 123 and 133 respectively and controls the current. An input clock signal is transmitted to every AND gate via a line 105, and the output of every CMOS TR is connected to a common output line to which the capacitance is connected as a load 150. Meanwhile, the TR 110, 120 and 130 are selectively used via the selection/control lines 161 to 163 and makes these TRs as the voltage dividers using the resistance components to select the resistance value. The selected value is combined with the capacitance, i.e., the load 150, so that a time constant that decides the shape of the output clock signal transition can be selected.</p> |
