摘要 |
A known phase-control loop comprises an oscillator having a controllable frequency, a frequency divider and a phase comparator which compares a reference signal (CKREF) with the signal at the output of the frequency divider and controls the frequency of the oscillator. The circuit also comprises, at the output of the oscillator, a phase shifter which supplies a signal (CKN0) at a multiple frequency of the input frequency and shifted in phase with respect to the signal of the oscillator, and a synchronizing module which may be simply constituted by a D flipflop with the input D connected to the output of the divider, and the input CLK connected to the output of the phase shifter, and which supplies a signal (CKREF0) at the frequency of the input signal (CKREF) but is locked at the output signal of the phase shifter.
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