发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS CHECK BIT FORMING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which check bits are buried enabling decision of the normal/abnormal conduction of a built-in ROM to be tested in a semiconductor integrated circuit without outputting an expected value and compression result each outside, and in which increase of the chip area is small. SOLUTION: This semiconductor integrated circuit 11 has a ROM part 12 which consists of a ROM cell 14 and its peripheral circuits, and incorporates in the ROM part 12 a compression means 15 which compresses ROM data read out from the ROM cell 14; at the last address of the ROM cell 14, check bits 15 which are for deciding normal/abnormal condition of the ROM data; are incorporated the compression result of the ROM data is added with the check bits 15 and recomposed into a single data value, with the value of this decompressed result outputted as the signal of the decision result of the normal/ abnormal conduction; and then, a specific value, at which the recomposed result of the compressed value of the normal ROM data becomes a normal decision result signal, is determined by preliminarily calculating backward with a theoretical simulator and used for the check bits 15.
申请公布号 JPH11242900(A) 申请公布日期 1999.09.07
申请号 JP19980045654 申请日期 1998.02.26
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 FURUKAWA HIROSHI
分类号 G01R31/28;G06F11/22;G11C29/00;G11C29/12 主分类号 G01R31/28
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