| 摘要 |
PROBLEM TO BE SOLVED: To contrive speeding-up in responsiveness faster than in the conventional device and also to attain saving in power consumption through lowered operating voltage, in the semiconductor memory device equipped with a memory cell to which both positive and negative bit lines are connected and with a sense amplifier which detects change in the voltage of this memory cell. SOLUTION: (1) In the sense amplifier 10, both bit lines 11, 12 are commonly connected to one end of the capacitor 4 through a first and a second short- circuiting circuits 1, 2 provided separately between the bit lines, with an inverting circuit 5 serially connected to the other end of the capacitor 4, with a third short-circuiting circuit 3 connected parallelly to this inverting circuit 5, and with a control circuit 6 installed controlling each of the first, second and third short-circuiting circuits 1-3. (2) This structure, having no inverter in the read circuit of the sense amplifier, can speed up the responsiveness. |
