发明名称 CIRCUIT AND METHOD FOR SELECTION OF TEST MODE
摘要 PROBLEM TO BE SOLVED: To reduce the number of terminals of an LSI chip, by a method wherein a usually used terminal is used temporarily as a test terminal so as to test an LSI. SOLUTION: In a test mode, a test mode signal TE is set at '1', and a selection switch circuit 6 is set to the side of '1'. After that, when test code signals S1, S2 are inputted from output terminals 12, 13, the test code signals S1, S2 are inputted to latch circuits L1, L2 through amplifier circuits 17, 19, AND circuits A1, A2 and flip-flops F1, F2. After that, when an LSI is reset, amplifier circuits 15, 16 are turned off, the latch circuits L1, L2 latch the test code signals S1, S2. After that, selection switch circuits 7, 8, 9 are changed over by the latched test code signals S1, S2, and a test signal is fetched from an output terminal Z via the selection switch circuit 6. When the test mode signal TE is set at '0', the selection switch circuit 6 is set to the side of '0', and a usual output signal is outputted from the terminal Z.
申请公布号 JPH11242072(A) 申请公布日期 1999.09.07
申请号 JP19980043822 申请日期 1998.02.25
申请人 TOSHIBA CORP 发明人 TAKAGI KENICHI
分类号 G01R31/28;G01R31/3185;H01L21/822;H01L27/04 主分类号 G01R31/28
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