发明名称 |
Semiconductor memory device having hierarchical input/output line structure and method for arranging the same |
摘要 |
A semiconductor memory device having a hierarchical input/output line structure and a method for arranging the same are provided. The semiconductor memory device includes a sub-array including a plurality of memory cells. The semiconductor memory device further includes a sense amplifier for sensing and amplifying the data of the memory cells of the sub-array. The semiconductor memory device further includes a sub-word line driver for driving the word lines of the memory cells. The semiconductor memory device further includes a local input/output line for receiving and transmitting the output signal of the sense amplifier. The semiconductor memory device further includes a global input/output line for receiving and transmitting the signal of the local input/output line. The semiconductor memory device further includes switching means for transmitting the signal of the local input/output line to the global input/output line in response to predetermined control signals. A conjunction area is formed in an intersecting area between the sense amplifier and the sub-word line driver. In particular, the switching means are separated and arranged in the conjunction areas in which the local input/output line intersects the global input/output line. A P driver and an N driver for driving the sense amplifier are arranged in the same conjunction.
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申请公布号 |
US5949697(A) |
申请公布日期 |
1999.09.07 |
申请号 |
US19970988289 |
申请日期 |
1997.12.10 |
申请人 |
SAMSUNG ELECTRONICS, CO., LTD. |
发明人 |
LEE, KYU-CHAN |
分类号 |
G11C11/409;G11C7/10;G11C8/14;G11C11/401;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):G11C5/02 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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