| 摘要 |
PCT No. PCT/US95/06255 Sec. 371 Date Jul. 14, 1995 Sec. 102(e) Date Jul. 14, 1995 PCT Filed Jun. 7, 1995 PCT Pub. No. WO96/41342 PCT Pub. Date Dec. 19, 1996A track address pattern embedded in the servo zones of a storage medium for representing a track address identification having a binary bit length "n". The track addresses pattern embedded in the medium is recoded from a Gray-code representation of the track address identification and has a code rate of n/(n+1), where n>/=2. The recoded track address pattern (or codeword) is modeled from a Gray-code representation wherein a plurality of bit cells corresponding to a track address of the data storage apparatus are recoded to include a parity bit selected to maintain a selected parity for the track address pattern. More particularly, when a "1" occurs in the same bit cell location in two adjacent track address patterns, then the parity on "1"s up until the same bit cell location is the same for both of the mth and the (m-1)th track address patterns and for the mth and the (m+1)th track address patterns. Furthermore, the codewords provide that the bit cells of an mth track address differ from the bit cells of an (m-1)th track address in exactly two bit cell locations, and that the bit cells of an mth track address differ from the bit cells of an (m+1)th track address in exactly two bit cell locations. One of the positions in which the neighboring codewords differ is the parity bit position.
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