| 摘要 |
The arrangement has an electric load and two semiconductor arrangements, which comprise respectively parallel circuits for limiting a voltage rise. A voltage level monitoring circuit (52, 36) in each semiconductor arrangement (30, 46) has a first input connected with a reference voltage, and a second input connected with the load output of the respective semiconductor arrangement, as well as over a capacitor (54,38) with the pole (64, 66) of the other semiconductor arrangement. The arrangement has an electric load and two semiconductor arrangements which comprise respectively parallel circuits for limiting a voltage rise. One of the semiconductor arrangements is connected with one of two load connections and a pole of an AC voltage source, and the other with the other load connection and the other pole of the AC voltage source. A voltage level monitoring circuit (52, 36) in each semiconductor arrangement (30, 46) is connected at its output with an evaluation unit. A first input of the monitoring circuit is connected with a reference voltage, derived from the voltage of the AC voltage source, and adjusted on the voltage at the load output of the respective semiconductor arrangement. A second input is connected with the load output of the respective semiconductor arrangement, as well as over a capacitor (54,38) with the pole (64, 66) connected at the other semiconductor arrangement of the AC voltage source.
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