发明名称 High-speed error correcting apparatus with efficient data transfer
摘要 <p>An error correcting apparatus includes a storing means for storing product code with n2 rows and n1 columns, an error correcting unit 5 that performs error correction for four code sequences simultaneously in parallel, and a bus control unit 2 for reading codes on four rows from the buffer memory 1 and transferring the codes to the error correcting unit 5. The bus control unit 2 reads and transfers four consecutive codes on each of four rows in order before shifting the reading position by four codes in the row direction. &lt;IMAGE&gt;</p>
申请公布号 EP0939403(A2) 申请公布日期 1999.09.01
申请号 EP19990301349 申请日期 1999.02.24
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 NAKATSUJI, FUMIO;HASHIMOTO, YUICHI
分类号 G06F11/10;G11B7/00;G11B20/10;G11B20/18;G11C29/00;H03M13/00;H03M13/11;H03M13/29;(IPC1-7):G11B20/18 主分类号 G06F11/10
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