| 摘要 |
A semiconductor integrated circuit has a self-oscillation circuit 5 for generating an internal clock signal ICK, a frequency division circuit 6 for generating a divided clock signal DCK based on an external clock signal CK, a switching circuit 7 connected to the self-oscillation circuit 5 and a frequency division circuit 6 and selectively outputting one of the internally clock signal ICK and the divided clock signal DCK in response to a control signal STBY, a controller 3 connected to the self-oscillation circuit 5 and the frequency division circuit 6 and the switching circuit 7, receiving a mode signal, and outputting the control signal STBY in accordance with the mode signal, when the mode signal is in a standby mode state, the self-oscillation circuit 5 is stopped and the switching circuit 7 selects the divided clock signal DCK, when the mode signal is in a normal operating state, the switching circuit 7 selects the internally clock signal ICK, and a charge pump circuit 8 receiving one of the internal clock signal ICK and the divided clock signal DCK and generating a high voltage Vh when the internal clock signal ICK is supplied through the switching circuit 7, and a voltage Vha different from the high voltage Vh when the divided clock signal DCK is supplied through the switching circuit 7. |
