发明名称 |
Direct memory access unit having a definable plurality of transfer channels |
摘要 |
Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.
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申请公布号 |
US5944800(A) |
申请公布日期 |
1999.08.31 |
申请号 |
US19970928558 |
申请日期 |
1997.09.12 |
申请人 |
INFINEON TECHNOLOGIES CORPORATION |
发明人 |
MATTHEIS, KARL-HEINZ;ROHM, PETER |
分类号 |
G06F13/28;(IPC1-7):G06F13/14 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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