发明名称 |
Semiconductor memory testing device |
摘要 |
In a small-size device, one input terminals of a plurality of AND circuits are connected in series. The other terminals of the plurality of AND circuits receive failure information held by a register circuit. Among the AND circuits, by changing values at the AND circuits which are connected in an output direction (i.e., most significant bit side) of an AND circuit receiving a failure bit and values at the AND circuits which are connected in an input direction (i.e., least significant bit side) of the AND circuit receiving the failure bit, a signal line associated with the failure bit is disconnected and signal lines are re-connected to adjacent signal lines including an extra line by selectors. Hence, a failure bit is compensated in a very simple structure.
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申请公布号 |
US5946247(A) |
申请公布日期 |
1999.08.31 |
申请号 |
US19980013062 |
申请日期 |
1998.01.26 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OSAWA, TOKUYA;MAENO, HIDESHI |
分类号 |
G01R31/3185;G11C29/08;G11C29/32;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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