发明名称 Load pole stabilized voltage regulator circuit
摘要 A voltage regulator with load pole stabilization is disclosed. An error amplifier has a non-inverting input receiving a reference voltage and an inverting input receiving a feedback voltage from the output of the voltage regulator. A gain stage has an input connected to the output of the error amplifier and an output connected to a pass transistor that provides current to a load. A variable impedance device such as a FET transistor configured as a variable resistor is connected between the input and output of the gain stage to provide variable zero to cancel the varying pole when the output current drawn by the load fluctuates. Consequently, the disclosed voltage regulator has high stability without a significant increase in power dissipation.
申请公布号 US5945818(A) 申请公布日期 1999.08.31
申请号 US19980098184 申请日期 1998.06.16
申请人 STMICROELECTRONICS, INC. 发明人 EDWARDS, WILLIAM E.
分类号 G05F3/26;G05F1/56;G05F1/565;G05F1/575;H03F3/343;(IPC1-7):G05F1/56 主分类号 G05F3/26
代理机构 代理人
主权项
地址