发明名称 MULTI-LAYER STRUCTURE OF SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
摘要 PROBLEM TO BE SOLVED: To prevent a decline of wiring reliability arising from a stress, in an area between upper and lower plugs in a multi-layer wiring structure of a semiconductor device having a stack structure. SOLUTION: In a multi-layer wiring structure causing a resistance variation due to long time storage at high temperature, a void 40 is observed in wiring 4 between an upper plug 3 and a lower plug 6. Parts 43, 44 between upper and lower plugs 3, 6 have crystal grains of smaller size than that of other parts, and have different plane orientation from that of other parts. For this reason, in order to raise wiring reliability, a wiring stress is lessened by shifting a center of contact surfaces between upper and lower plugs, or sputtering temperature is set so as not to give rise to crystal grain boundaries between upper and lower plugs, when a wiring layer of aluminum or an aluminum alloy is formed.
申请公布号 JPH11238801(A) 申请公布日期 1999.08.31
申请号 JP19980280141 申请日期 1998.10.01
申请人 MATSUSHITA ELECTRON CORP 发明人 DOMAE SHINICHI;MASUDA YOJI;KATO YOSHIAKI;YANO KOSAKU
分类号 H01L21/285;H01L21/28;H01L21/768;H01L23/522;(IPC1-7):H01L21/768 主分类号 H01L21/285
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