发明名称 |
Zero power high speed configuration memory |
摘要 |
A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
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申请公布号 |
US5946267(A) |
申请公布日期 |
1999.08.31 |
申请号 |
US19970978286 |
申请日期 |
1997.11.25 |
申请人 |
ATMEL CORPORATION |
发明人 |
PATHAK, SAROJ;ROSENDALE, GLEN A.;PAYNE, JAMES E.;HANGZO, NIANGLAMCHING |
分类号 |
G11C16/02;G11C7/10;(IPC1-7):G11C8/00 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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