发明名称 Memory testing apparatus
摘要 There is provided a memory testing apparatus having, for a high speed device testing, a failure data display controller for memory test including a display apparatus for displaying positions of failure memory cells based on failure data obtained by testing of a memory. After the test is completed, the failure data stored in a failure memory for storing failure data are transferred to a failure buffer memory for temporarily storing failure data provided in the failure data display controller. The failure data stored in the failure buffer memory are converted and transferred to the display apparatus. During the time period when the next device is being tested, the failure cell positions of the previously tested device are displayed on the display apparatus.
申请公布号 US5946250(A) 申请公布日期 1999.08.31
申请号 US19990252634 申请日期 1999.02.19
申请人 ADVANTEST CORPORATION 发明人 SUZUKI, TOSHIKAZU
分类号 G01R31/28;G01R31/3193;G11C29/44;G11C29/56;(IPC1-7):G11C7/00 主分类号 G01R31/28
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