| 摘要 |
A first load 10 is connected between a signal terminal 12 for driving an output transistor 11 and a highest potential VCC. A first switch 7 is connected in parallel with the first load 10. A second switch 8 is connected between the signal terminal 12 and a current source 14. A third switch 9 is connected between the highest potential VCC and the current source 14. The first to third switches are on-off operated according to a CMOS level input to provide an ECL level from an output transistor. The current source 14 includes a bipolar transistor 1 and a resistor 2, thereby occupying only a small area and precluding output fluctuations due to fluctuations in manufacture.
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