| 摘要 |
It is an object of the present invention to provide a ferroelectric memory device having a high integration and capable of maintaining nonvolatility. A threshold voltage Vth of a ferroelectric memory element is set at value slightly higher than a voltage -V1. A voltage 0V is applied as a gate voltage VG when the stored data is read out. A voltage V1 is generated at a MOS capacitor CMOS if the data "High" is stored and the voltage -V1 is generated at the MOS capacitor CMOS if the data "Low" is stored. The stored data is read out by detecting a drain current during generation of the voltages. Also, a voltage 0V is applied as the gate voltage VG when stand-by operation is carried out. In this way, variation of the gate voltage VG caused by switching ON and OFF of a power source can be prevented. So that, nonvolatility of the ferroelectric memory device can be maintained as a result of preventing spontaneous polarization of a ferroelectric capacitor Cferro. Further, it is not necessary to provide a circuit for generating a voltage for using read out the data to the ferroelectric memory device. So that, integration of the ferroelectric memory device can be increased.
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