发明名称
摘要 <p>PURPOSE:To execute the encoding processing and decoding processing optimum to the characteristic of information at high speed by having a first mode to transmit a predictive coding code outputted by a memory circuit including a lookup table and a second mode to transmit data to show a decoding table corresponding to an above-mentioned lookup table. CONSTITUTION:An input sample value from an input terminal 101 and a predicted value from a D type F/F 104 are supplied to a RAM 105 as reading address control data. A DPCM code is inputted to a synchronizing and ID adding circuit 109, synchronous data and ID data are added and made into a data system. The data system outputted by the circuit 109 is sent to a transmission line by a terminal 111. In a decoder, a table identification circuit 131 identifies that the DPCM code is inputted by the identification code separated by a synchronizing and ID separating circuit 123. To a RAM 127, a decoding table corresponding to the processing of the RAM 105 is written and the decoding value is outputted to an output terminal 130.</p>
申请公布号 JP2941820(B2) 申请公布日期 1999.08.30
申请号 JP19880280125 申请日期 1988.11.05
申请人 KYANON KK 发明人 YAGISAWA TOSHIHIRO;ISHIKAWA TAKASHI
分类号 H04N19/50;H03M7/32;H03M7/38;H04N19/423;H04N19/46;H04N19/70;(IPC1-7):H03M7/38 主分类号 H04N19/50
代理机构 代理人
主权项
地址