| 摘要 |
It was heretofore difficult to perform specific operations while at the same time avoiding a delay in exception processing and preventing a drop in performance. A pipeline comprises five stages of fetch I, decode R, execute A, memory access M, and register write W. An operation initiation instruction (instruction 1) and an operation result fetch instruction (instruction 2) are separately provided. Instruction 1 only causes an initiation, and then ends. Instruction 2 waits for the operation of instruction 1 to complete at stage R. If a request for exception processing is issued at this time, instruction 2 is canceled and the processing is performed since stages I and R do not modify the state of hardware. The execution of the operation also continues during this time. After exception processing, instruction 2 is re-executed from stage I. |
