| 摘要 |
A bus bridge which intercepts synchronization events and selectively flushes data in buffers within the bridge is disclosed. The bridge insures data consistency by actively intercepting synchronization events, including, interrupts, processor accesses of a control status registers, and I/O master accesses of shared memory space. Interrupt signals may be routed through the bridge, which includes a bridge control unit comprised of state machine logic for managing data transfers through the bridge. In response to an interrupt signal from an agent on a bus, the bridge control unit flushes posted data before allowing a processor to process the interrupt signal. The bridge control unit further requires that the bridge complete all posted writes generated from a first bus before the bridge accepts a read generated from a second bus. The bridge control unit additionally insures strict ordering of accesses through the bridge. Data consistency is thereby realized without requiring the bridge to participate in the cache coherency protocol of the primary bus.
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