Efficient self-timed marking of lengthy variable length instructions
摘要
A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.
申请公布号
US5941982(A)
申请公布日期
1999.08.24
申请号
US19970997461
申请日期
1997.12.23
申请人
INTEL CORPORATION
发明人
GINOSAR, RAN;KOL, RAKEFET;STEVENS, KENNETH SCOTT;BEEREL, PETER A.;YUN, KENNETH YI;MYERS, CHRISTOPHER JOHN;ROTEM, SHAI