| 摘要 |
A division circuit which can shorten a critical path for division and can perform the division at a high speed, provided with a 1's complement processor for outputting a complement of 1 of a divisor when the divisor is negative; an adder for adding "1" to the output from the complement processor and making the result of addition an absolute value; a priority encoder for calculating a logarithmic value comprised of an integer value of a logarithm of 2 of the value output from the 1's complement processor, a shift processor for shifting the absolute value in accordance with the logarithmic value, making the shift processing value a mantissa when the MSB of the shift processing value is "1", and making the shift processing value with an MSB replaced by "1" the mantissa when the MSB of the shift processing value is "0", and a subtractor for determining the shift amount in response to the MSB of the shift processing value of the shift processor. |
