| 摘要 |
A non-volatile latch is disclosed which includes four PMOS floating gate memory cells arranged in a 2x2 matrix. Binary data values are written to the latch by the threshold voltage of the cells, where a first binary value is written by programming all the cells, and the second binary value is written by leaving all the cells in an erased state. Thus, since a program operation is required when writing only one of the binary value, high program voltages and floating gate charge times are eliminated when writing the other binary value. After a read operation in which the binary value stored in the cells is provided as output, this binary value is automatically latched in a latch circuit. In this manner, subsequent reads to the latch do not require accessing the cells.
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