发明名称 CONTROL DATA SWITCHING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a control data switching circuit coping with changes in large controlled variables. SOLUTION: When a controlled data 1 is taken as a controlled data whose controlled value is small, a controlled data whose controlled value is further smaller is taken as a controlled data 4. When switching request (a) is entered, a switching timing generation section 5 generates a switching signal (b) to control a 4→1 selector 6. The 4→1 selector 6 outputs controlled data 1-4 to a switching controlled section. The 4→1 selector 6, when switching the controlled data 1 to a controlled data 2, selects a controlled data 3 for a constant time, and when switching the controlled data 2 to the controlled data 1, selects the controlled data 4 for a constant time. The switching timing generation section 5 transmits the switching signal (b) synchronized with the read-out timing of memories 1-4 in replay to the switching request from an external section.
申请公布号 JPH11229923(A) 申请公布日期 1999.08.24
申请号 JP19980027614 申请日期 1998.02.09
申请人 NEC ENG LTD 发明人 KAWABUCHI SHIGERU
分类号 F02D45/00;F02D41/04;(IPC1-7):F02D41/04 主分类号 F02D45/00
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