发明名称
摘要 <p>To form a means preventing a logic circuit from outputting wrong data at uncontrolled, unstable state of power turn-on in a control circuit. The control circuit has two logic circuits therein and takes negative OR or negative AND of output thereof. A first input terminal is connected to an input of an inverter circuit and a second logic circuit; the output of the inverter circuit is connected to the input of the first logic circuit; a second input terminal is connected to the first logic circuit and the second logic circuit; outputs of the first logic circuit and the second logic circuit are connected to inputs of a gate circuit; the output of the gate circuit is connected to a output terminal; and the first logic circuit and the second logic circuit output the opposite level to each other, positive and negative.</p>
申请公布号 JP2936474(B2) 申请公布日期 1999.08.23
申请号 JP19980052479 申请日期 1998.03.04
申请人 SEIKOO INSUTSURUMENTSU KK 发明人 ISHII TOSHIKI
分类号 G06F1/26;G11C11/413;H03K19/003;(IPC1-7):H03K19/003 主分类号 G06F1/26
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