发明名称
摘要 <p>PURPOSE:To reproduce block synchronism with high accuracy at high speed by canceling the scramble of a code word by adding a pseudo random sequence, and establishing the block synchronism by decoding the canceled code word. CONSTITUTION:A block synchronism reproducing circuit 106 performs block synchronism reproducing with received data (a) and a block (b). Namely, when the end of a most certain BIC(block synchronism identification code) detecting position is recognized, a BIC detect signal (c) is outputted to a PN signal generating circuit 108. The signal generating circuit 108 outputs a PN signal (h) to an XOR circuit 110. The circuit 110 outputs descrambled data to a delay circuit 112 by exclusively ORing the received data (a) and the PN signal (h). When the code word in the received data (a) is written onto a frame memory 114 by this procedure, first lateral decode processing is performed by a decoding circuit 116. This operation is controlled by a control circuit 118, the decoding circuit 116 outputs a signal (d) to the reproducing circuit 106, and a decode end signal S is outputted.</p>
申请公布号 JP2937744(B2) 申请公布日期 1999.08.23
申请号 JP19940094216 申请日期 1994.05.06
申请人 SANYO DENKI KK;NIPPON HOSO KYOKAI 发明人 YAMASHITA SHUGO;TOMITA YOSHIKAZU;KURODA TOORU;TAKADA MASAYUKI;ISOBE TADASHI;YAMADA TSUKASA
分类号 H04J13/00;G06F21/10;H04B1/7073;H04L7/00;(IPC1-7):H04J13/02 主分类号 H04J13/00
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