| 摘要 |
A memory device for storing and outputting information includes a plurality of memory matrices, each memory matrix containing a plurality of transistors having a drain, a source, and a gate and the plurality of transistors are arranged in a plurality of levels that proceed from a lowest to a highest level. A plurality of single bit shift registers is also provided for producing a serial output, each shift register having a memory input and an associated memory matrix, wherein the memory input of each shift register is electrically connected to the sources of the transistors in the highest level of the shift register's associated memory matrix. A plurality of address lines for receiving a decode signal function, a load signal, and a clock as well as an output line for transmitting the serial output of the plurality of shift registers is also provided. Embodiments of the invention may employ any number of shift registers and memory matrices independent of the number of available address lines. <IMAGE> |
