Multiple voltage MOS transistor production for sub-micron applications requiring selection between two or more voltages

摘要

The multiple voltage MOS transistor is produced by large angle tilt ion implantation into one or more high voltage MOS regions (HV MOS) to form buffer layers which overlap lightly doped drain regions of the HV MOS. Independent claims are also included for the following: (i) production of a MOS transistor, which allows voltage selection between two values by means of high and low voltage (HV, LV) MOS polysilicon gates formed on an active substrate region, by ion implantation to form several lightly doped regions alongside the gates, formation of a photoresist layer which exposes the HV MOS, large angle tilt ion implantation to form buffer layers which overlap the lightly doped regions, removal of the photoresist layer, formation of gate sidewall spacers and ion implantation to form heavily doped source/drain regions alongside the sidewall spacers; and (ii) a similar process for production of a MOS transistor which allows selection between several voltages by means of two HV MOS and one LV MOS, each having an LDD structure, formed on an active substrate region.