METHOD AND APPARATUS FOR MINIMIZING ASYNCHRONOUS TRANSMIT FIFO UNDER-RUN AND RECEIVE FIFO OVER-RUN CONDITIONS

摘要

A circuit adapted to a first-in/first-out device ("FIFO") (310) is disclosed. The circuit includes a counter (320) and a first end of packet detector (315) that is coupled to the counter (320). The first end of packet detector (315) increments the counter (320) if an end of packet is detected at an input of the FIFO (310). The circuit also includes a second end of packet detector (330) coupled to the counter (320). The second end of packet detector (330) decrements the counter (320) if an end of packet is detected at an output of the FIFO (310). A detector circuit (335) is coupled to an output of the counter (320) and requests a bus transaction in response to the output of the counter (320). In another aspect, the present invention is a method of preventing data over-run errors in a receive FIFO.