发明名称 Method of reducing metal voids in semiconductor device interconnection
摘要 <p>The occurrence of defects in interconnect metal structure is reduced or eliminated by a method wherein a semiconductor substrate having a dielectric layer, a metal-containing electrically conductive layer and a patterned photoresist layer, the metal-containing electrically conductive layer overlying the dielectric layer and the photoresist layer overlying the conductive layer such that portions of the conductive layer are exposed, is treated using a sequence of at least four reactive ion etching environments each having a different etchant composition from the previous and/or subsequent environment. The invention is especially applicable for metal interconnect structures having aluminum and/or copper as the primary conductive layer. <IMAGE></p>
申请公布号 EP0936666(A2) 申请公布日期 1999.08.18
申请号 EP19980310521 申请日期 1998.12.21
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 NAEEM, MUNIR-UD-DIN
分类号 H01L21/302;H01L21/3065;H01L21/3213;H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/302
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