| 摘要 |
<p>Biasing system of a bitline in a sense circuit for a non-volatile wide supply voltage range memory, in particular an EEPROM type memory, comprising an amplifier with two inputs to which two current sensing branches are connected, one current being relative to the memory cell and the other one taken from a reference circuit, of the type using a transistor for defining a biasing voltage onto a bitline, said transistor being biased through a voltage obtained by means of a feedback circuit connected to the relevant bitline. According to the invention, in order to supply the said biasing voltage (VBL), said transistor (N1) is in turn biased by a voltage (VGN1), which is in turn obtained through a circuit wherein a stable current (IP) flows, independent from the supply voltage (VDD) value, so that said biasing voltage (VBL) is independent from the supply voltage (VDD) value. <IMAGE></p> |
