发明名称 Integrated circuit passively biasing transistor effective threshold voltage and related methods
摘要 An integrated circuit preferably includes a plurality of enhancement-mode MOSFETs on a substrate with each MOSFET having an initial threshold voltage, and a plurality of resistors connected to define a resistor voltage divider for passively biasing the MOSFETs to produce an absolute value of an effective threshold voltage of each MOSFET to be lower than an absolute value of the initial threshold voltage. Accordingly, the effective threshold voltages may set to below a predetermined value, and lower supply voltages thereby readily accommodated. For integrated circuits having all n-channel MOSFETs, the threshold voltages are positive, and the voltage divider can be set accordingly. The invention is advantageously also used in CMOS integrated circuits having both p-channel and n-channel MOSFETs. The resistor voltage divider may preferably be set or trimmed after forming the MOSFETs. Accordingly, in one embodiment heat fusible links, are operatively connected to the first plurality of resistors for permitting selective electrical connection of predetermined ones of the resistors. In another variation, the voltage divider may be set by at least one laser trimmed resistor having a trimmed resistance to produce a desired effective threshold voltage for each MOSFET. Method aspects of the invention are also disclosed.
申请公布号 US5939934(A) 申请公布日期 1999.08.17
申请号 US19960758933 申请日期 1996.12.03
申请人 STMICROELECTRONICS, INC. 发明人 SO, JASON SIUCHEONG;CHAN, TSIU CHIU
分类号 H01L27/02;H01L27/06;(IPC1-7):G05F7/10 主分类号 H01L27/02
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