| 摘要 |
PROBLEM TO BE SOLVED: To reduce a skew due to the repeating buffers from the input point for a clock signal in the semiconductor integrated circuit to a distribution destination. SOLUTION: The circuit is equipped with a 2nd PLL circuit 102 which receives a clock signal of frequency lower than the clock signal inputted to the circuit block 101 of a terminal from outside and a 1st PLL circuit 103 which receives a clock signal generated by the 2nd PLL circuit 102, and the externally inputted clock signal is supplied to the 1st PLL circuit 103 through the 2nd PLL circuit 102 and supplied to distribution destinations of respective terminals in the circuit block 101. Since the clock signal of low frequency is inputted from outside, the number of the stages of repeating buffers from the input point for the clock signal to the distribution destinations can be reducible. |
