发明名称 |
System and method for performance monitoring of instructions in a re-order buffer |
摘要 |
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
|
申请公布号 |
US5938760(A) |
申请公布日期 |
1999.08.17 |
申请号 |
US19960767655 |
申请日期 |
1996.12.17 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LEVINE, FRANK ELIOT;MOORE, ROY STUART;ROTH, CHARLES PHILIP;WELBON, EDWARD HUGH |
分类号 |
G06F11/34;(IPC1-7):G06F11/28 |
主分类号 |
G06F11/34 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|