| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock generating circuit that receives a 1st clock with a prescribed frequency and generates a 2nd clock with a different frequency, but with the same phase. SOLUTION: In the proposed clock generating circuit, when a frequency of a clock ck1 is not an integer multiple of a frequency of a clock ck2, an error amount integration means 10 integrates an error of a phase of the clocks ck1, ck2, and outputs a time interval extension instruction signal S10 when the integrated amount reaches an amount equal to one period of the clock ck1. A time interval generating means 20 generates an edge timing signal S20 of the clock ck2 from the clock ck1, based on a parameter P3, but generates a timing signal S20 with an interval more by '1' than the parameter P3 when receiving the time interval extension instruction signal S10 and gives it to a clock generating means 30. The clock generating means 30 receives the timing signal S20 and inverts the stored value and generates the clock ck2. |
