| 摘要 |
PROBLEM TO BE SOLVED: To make it possible to successively detect and output the number of times that zero data continue and non-zero data following after the zero data by accumulating the output of a shifter for switching the presence/absence of the execution of the shift of the output of a comparator circuit. SOLUTION: When first and second data do not match with each other, the comparator circuit 1A makes identity signals a low level and a flag register 3A performs latching synchronized with the rise of an operation clock. At the time, the shifter 4A does not shift the value of a first register 2A, the value of the first register 2A is outputted to a second register 5A as it is and a latching is performed synchronizedly with the rise of the operation clock there. A selection circuit 6A outputs the value 0 when selection signals are at the low level and selects the output of a third register 8A for latching the output of an addition circuit 7A synchronized with the rise of the clock when they are at a high level. The addition circuit 7A inputs the respective outputs of the register 5A and the selection circuit 6A, adds both and outputs them to the third register 8A to be accumulated. |
