| 摘要 |
This invention relates to an erase circuit of flash memory device comprising an erase verifying block unit outputting a final loop signal when an chip erasing operation is not performed within a predetermined time, a high voltage detection unit outputting a high voltage signal in response to an inverted chip erase signal, a buffer outputting an output enable signal in response to an inverted output enable signal, a control unit outputting a first to third select address signals in response to said final loop signal, inverted high voltage signal and output enable signal, an address counter unit outputting data in response to said first to third select address signals, an output multiplexor outputting one of a sense amp output signal, hardware flag and data read from said address counter unit in response to said first to third select address signals, sense amp control signal and hardware flag signal.
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