SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a non-volatile memory having hierarchical bit line structure realizing high speed operation and a non-volatile memory having hierarchical bit lien structure enabling high speed read-out operation without increasing manufacturing process. SOLUTION: In a batch erasing type non-volatile memory having hierarchical bit lien structure, each of plural sub-bit lines constituting hierachical bit lines is connected to corresponding main bit lines through a first selection MOSFET 1 of which a gate insulation film is formed thinly and which is used for only read-out operation, and a second selection MOSFET 2 of which a gate insulation film is formed thickly and which is used for writing operation, while the prescribed bias voltage is applied to a drain or a gate so that high voltage exceeding its breakdown strength is not applied to a gate insulation film of the first selection MOSFET 1 at the time of writing operation.