发明名称 |
Multi-bank DRAM suitable for integration with processor on common semiconductor chip |
摘要 |
A dynamic random access memory DRAM includes banks which are driven to active or inactive states independently of each other. Activation/inactivation of these banks are controlled by row controllers operating independently of each other, whereby a page or word line can be selected in each of the banks, a page hit rate can be increased, and the number of array precharge operation times in a page error as well as power consumption can be reduced in response. Thus, the cache hit rate of a processor having a built-in DRAM is increased and power consumption is reduced.
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申请公布号 |
US5940342(A) |
申请公布日期 |
1999.08.17 |
申请号 |
US19980080276 |
申请日期 |
1998.05.18 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YAMAZAKI, AKIRA;DOSAKA, KATSUMI |
分类号 |
G06F12/08;G06F12/00;G06F12/02;G06F12/06;G11C8/12;G11C11/401;G11C11/406;G11C11/407;G11C11/408;G11C11/409;(IPC1-7):G11C7/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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