发明名称 Parallel testing of CPU cache and instruction units
摘要 A method for testing CPU microprocessors having internal cache involves testing one IU and a portion of the internal cache, then loading a cache test routine to the tested portion of internal cache and causing that routine to be executed by the tested IU to test the previously untested portion of the internal cache while simultaneously testing any other IUs and circuitry on the CPU microprocessor. A system is disclosed for performing the method.
申请公布号 US5940588(A) 申请公布日期 1999.08.17
申请号 US19960685041 申请日期 1996.07.23
申请人 KIKINIS, DAN 发明人 KIKINIS, DAN
分类号 G06F11/22;G01R31/319;G06F11/267;G11C29/08;G11C29/12;(IPC1-7):G06F11/00;G06F11/30 主分类号 G06F11/22
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