发明名称 |
Memory architecture and systems and methods using the same |
摘要 |
A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.
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申请公布号 |
US5940329(A) |
申请公布日期 |
1999.08.17 |
申请号 |
US19970992416 |
申请日期 |
1997.12.17 |
申请人 |
SILICON AQUARIUS, INC.;SILICON SA |
发明人 |
SEITSINGER, STEPHEN EARL;HOLLAND, WAYLAND BART |
分类号 |
G11C7/10;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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