发明名称 |
Circuit and method for a memory device with p-channel isolation gates |
摘要 |
A circuit and method for limiting voltage swing on the complementary bit lines of a memory device. Complementary bit lines of the memory device are coupled to a sense amplifier through first and second p-channel isolation devices. A low voltage is applied to a gate of the p-channel isolation devices to activate the p-channel isolation devices such that one of the first and second p-channel isolation devices establishes the low logic level on one of the complementary bit lines at a voltage that limits the swing on the complementary bit lines.
|
申请公布号 |
US5940339(A) |
申请公布日期 |
1999.08.17 |
申请号 |
US19980139852 |
申请日期 |
1998.08.25 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
SHIRLEY, BRIAN M.;CASPER, STEPHEN L. |
分类号 |
G11C7/06;G11C11/4091;(IPC1-7):G11C7/02;G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|