发明名称 NETWORK FOR TRANSFERRING CONSECUTIVE PACKETS BETWEEN PROCESSOR AND MEMORY WITH A REDUCED BLOCKING TIME
摘要 For making in a parallel computer system an interconnection network transfer data sequences, each composed of consecutive packets, from input ports (17) to a destination port indicated among output ports (19) by a routing address specified by a leading packet of each data sequence, control registers (31) hold the routing address of a privileged sequence determined by arbiters (39) in response to such addresses held in the control registers and stored in control buffers (33), Data of the consecutive packets of the privileged sequence are simultaneously stored in and produced from data buffers (37). Controlled by the arbiters, input selectors (41, 43) select the data for delivery to the destination port through output buffers (55) and output selectors (57) controlled by a selector operating arrangement (59-63). When the data of the consecutive packets are not yet wholly stored in the data buffers, the input selectors select only those already stored in the data buffers and then select the data of remaining ones of the consecutive packets as soon as they reach the data buffers.
申请公布号 CA2152637(C) 申请公布日期 1999.08.17
申请号 CA19952152637 申请日期 1995.06.26
申请人 发明人 DATE, YUUKI
分类号 G06F15/167;G06F15/17;G06F15/173;(IPC1-7):G06F15/16;G06F13/14 主分类号 G06F15/167
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