发明名称 CLAMP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To lock an input signal to a clamp setting level at a high speed and then to stably store the signal. SOLUTION: In the case a level of an analog signal line 11 is considerably smaller than a clamp setting level, this clamp circuit connects a plurality of current sources 21 in a current source group 14 to the analog signal line 11 to rapidly increase the level of the analog signal line 11 so as to clock the level to the clamp setting level. Furthermore, when the level of the analog signal line 11 is locked to the clamp setting level, one current source 21 is used to adjust the level of the analog signal line 11. Thus, the voltage increase due to an input impedance to a pre-stage of a capacitor 17 is suppressed so as to reduce voltage fluctuation of the analog signal line 11 attended with on/off switching of a switch 22.
申请公布号 JPH11225032(A) 申请公布日期 1999.08.17
申请号 JP19980023698 申请日期 1998.02.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HASHIMOTO KOKICHI
分类号 H04N5/18;H03G11/00;H03K5/007;H04N9/72 主分类号 H04N5/18
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