发明名称
摘要 <p>PURPOSE:To simplify a test pattern by using a load transistor or resistor for test, which removes the open defect of parallel transistors forming a NOR gate or a NAND gate for cosntituting a decoder. CONSTITUTION:There is a decoder circuit which is constituted of a NOR gate, wherein a load MOS transistor 29 that is controlled with a test signal T is arranged. When one of transistors 21-24 becomes defective by opening, the output Oi becomes the low level intrinsically in the conventional device because of the defective transistor. In this testing circuit, however, the output Oi becomes the high level with the load transistor 29, and the defect is judged in the test.</p>
申请公布号 JP2933444(B2) 申请公布日期 1999.08.16
申请号 JP19920177842 申请日期 1992.07.06
申请人 NIPPON DENKI AISHII MAIKON SHISUTEMU KK 发明人 KAMATANI MICHITOKU
分类号 G01R31/28;G11C17/18;G11C29/00;G11C29/12;G11C29/14;(IPC1-7):G01R31/28 主分类号 G01R31/28
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