| 摘要 |
A clocking scheme is provided which uses an external clock signal having a frequency F, and generates an internal master clock signal equal having a frequency lower than (e.g., +E,fra 1/2+EE ) F. The internal master clock signal operating at, for example, half the speed of the external clock is routed throughout a device to components on the device requiring a clock signal (e.g., input or output buffers in a synchronous memory product). A stream of narrow pulses corresponding to rising and falling edges of the internal master clock signal are locally generated for those components which require a clock signal at full frequency. This stream of narrow pulses has a frequency of F.
|
