| 摘要 |
A process of manufacturing a semiconductor device with a double-recessed gate field effect transistor, comprising the formation, on a substrate (1), of an active layer (3) of a semiconductor material and a first dielectric layer (D1), and further comprising the steps of: forming a second dielectric layer (R), forming an aperture (A0) in the second dielectric layer (R), then a first opening (A1) in the first dielectric layer (D1) having a same first width, while forming a second opening (A2) in the second dielectric layer having a second width larger than the first width, and then etching a preliminary recess (A4) in the subjacent semiconductor layer through said first opening (A1) having said first width, enlarging said first opening (A1) in the first dielectric layer (D1) to form a third opening (A3) having a third width larger than the second width, and then etching the semiconductor layer through said preliminary recess (A4) to form a deeper central recess (A6) having substantially said first width while etching a shallower peripheral recess (A5) substantially having said third width through said third opening (A3), and depositing through said second opening (A2) a gate metal material (8) having substantially said second width and extending over said central deeper recess (A6) and partially over said peripheral shallower recess (A5).
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